Recently, with the increase of operating speed (operating clock frequency) of CMOS LSI products, larger numbers of LSI products, each having a PLL (phase-locked loop) circuit, are manufactured and sold. The degree of accuracy demanded of the PLL circuit nowadays has become increasingly higher.
In the conventional charge-pump type PLL circuit, phase offset persists, so that variations in for example, temperature, power supply voltage, or fabrication process, significantly affect the circuit characteristic of the PLL circuit. Hence, the improvement of this situation in the charge-pump type PLL circuit is required.
FIG. 10 is a diagram illustrating an example of the configuration of a conventional charge-pump type PLL circuit (see Non-Patent Document 1). Referring to FIG. 10, the conventional charge-pump type PLL circuit includes a phase frequency detector (PFD) 10′, a charge pump circuit 20, and a voltage-controlled oscillator (VCO) 30. An output Vout of the VCO 30 is fed back as an input to the phase frequency detector 10′. The phase frequency detector (PFD) 10′ compares the phase of an output signal Vout with that of an input signal Vin, and outputs an UP signal UP, its complementary signal UPb, a DOWN signal DN and its complementary signal DNb. Of these, the signals UPb and DN are supplied to the charge pump circuit 20. The phase frequency detector (PFD) 10′ includes a D-type flip-flop with reset 11, a D-type flip-flop with reset 12, and AND circuit 13. The D-type flip-flop 11 has a data input terminal D connected to a power supply VDD, has a clock input terminal CK supplied with Vin, and samples a signal (HIGH LEVEL) at the data input terminal D responsive to the rising edge of Vin to output UP at a high level and UPb at a low level from a non-inverting output terminal Q and from an inverting output terminal QB, respectively. The D-type flip-flop 12 has a data input terminal D connected to the power supply VDD, has a clock input terminal CK supplied with Vout, and samples a signal at the data input terminal D responsive to the rising edge of Vout to output DN at a high level and DNb at a low level from the non-inverting output terminal Q and at the inverting output terminal QB, respectively. The AND circuit 13 receives UP and DN as inputs. An output signal (reset) of the AND circuit 13 is supplied to reset terminals R of the D-type flip-flops 11 and 12. When UP and DN are high, the output signal (reset) from the AND circuit 13 becomes high and the D-type flip-flops 11 and 12, which receive the high level reset signal from the AND circuit 13 at respective reset terminals R, are reset, as a result of which outputs UP and DN are reset to a low level, while respective complementary signals UPb and DNb are reset to a high level.
The charge pump circuit 20 includes pMOS transistors Pa1 and Pa2, nMOS transistors Na1 and Na2, and a capacitor 21. The pMOS transistor Pa1 has a source and a gate connected to the power supply VDD and to Vb2 (bias voltage), respectively. The pMOS transistor Pa2 has a source connected to the drain of the pMOS transistor Pa1 and has a gate supplied with Upb. The nMOS transistor Na2 has a drain connected to the drain of the pMOS transistor Pa2 and has a gate supplied with DN. The nMOS transistor Na1 has a drain connected to the source of the nMOS transistor Na2, has a gate supplied with Vb1 and has a source connected to the ground (GND). With this charge pump circuit 20, when UP is high and UPb is low, the pMOS transistor Pa2 is turned on to charge the capacitor 21 by the source current Isource supplied from the pMOS transistor Pa1 constituting a current source. Conversely, when DN is high, the nMOS transistor Na2 is turned on to discharge the capacitor 21 by the sink current Isink supplied from the nMOS transistor Na1 constituting a current source. The pMOS transistor Pa1 and the nMOS transistor Na1 receive at gates thereof bias voltages Vb2 and Vb1, respectively, such that the source current Isource and the sink current Isink will be as approximately equal to each other as possible. The respective timings at which the source current Isource and the sink current Isink flow are adjusted by the on time of the transistors Pa2 and Na2, which are on/off controlled by the signals UPb and DN, respectively. The terminal voltage of the capacitor 21 is supplied as the control voltage Vcont to the VCO 30.
The Patent Document 1 shows, a charge pump circuit comprising a current correcting circuit as shown in FIG. 12 is disclosed. This charge pump circuit operates as follows. When charging/discharging the capacitor in an LPF (loop filter), using UP and DN pulses output from a phase comparator, the difference between the charging current and the discharge current, resulting from the offset between output impedances of a pMOS transistor P12 and an nMOS transistor N12, is extracted and corrected so as to make the charging current and the discharge current equal to each other by a sense amplifier (AMP) 5. An output of the sense amplifier (AMP) 5 is fed back to pMOS transistors P12 and P14 to render the control voltage Vcont constant or to make Vcont to be kept in a preset voltage width. P13 and P11 are pMOS transistors, N11 and N13-N16 are nMOS transistors and I11 is a current source.
The Patent Document 2 discloses a PLL circuit including a pulse adjustment unit between a phase comparator and a charge pump and a pulse width adjustment unit for controlling the pulse width of UP and DOWN pulse signals output from the phase comparator to the charge pump to enable the lock in time to be reduced.
The Patent Document 3 discloses a PLL circuit including a feedback loop, comprised of a phase comparator for comparing the phase of a reference clock with that of a feedback clock, a charge pump, a loop filter and an oscillator, a pulse generator supplied with the reference clock and the feedback clock, and a pulse width decision circuit, and configured for adjusting the amount of phase correction consistent with the ratio of the delay in the feedback loop and the interval of the phase comparision.
The Patent Document 4 discloses a PLL circuit in which a reset signal of a phase comparator is delayed for decreasing a phase insensitive zone in a phase comparator.
The Patent Document 5 discloses the configuration of a PLL circuit in which two current source circuits are provided in a circuit for generating the current or the voltage consistent with the phase difference detected by a phase comparator, the operating current in the circuit is increased to cause a high gain operation of the circuit in effecting frequency pull-in, and in which the operating current in the circuit is decreased to cause high gain operation of the circuit in effecting phase matching.
The Patent Document 6 discloses, as the configuration for preventing a PLL circuit from being locked with a phase shift being remained, the configuration of a charge pump including a PNP transistor for current setting, an NPN transistor for current adjustment, and a feedback amplifier, in which no offset current flows through a filter even in case the output terminal voltage is varied, such as to maintain the balance of the charging current and the discharge current for a filter.
The Patent Document 7 is a diagram illustrating the configuration in which there are provided a steady-state phase error detection unit for detecting the phase difference between a reference clock and a VCO output clock signal, means for outputting a control signal for detecting the steady-state phase error only when the PLL circuit is in a pull-in state to control a steady-state phase error detection unit, and a load circuit means for adding a load to a reference clock line and to a feedback line from the VCO responsive to the steady-state phase error.
[Non-Patent Document 1]
Bahzad Razavi, translated by Tadahiro Kuroda, ‘Designing of Analog CMOS Integrated Circuits, Application’, published by MARUZEN, Mar. 30, 2003, pages 667-691
[Patent Document 1]
Japanese Patent Kokai Publication No. JP-P2003-87115A
[Patent Document 2]
Japanese Patent Kokai Publication No. JP-P2000-349626A
[Patent Document 3]
Japanese Patent Kokai Publication No. JP-P2002-141798A
[Patent Document 4]
Japanese Patent Kokai Publication No. JP-P2004-64742A
[Patent Document 5]
Japanese Patent Kokai Publication No. JP-A-11-205133
[Patent Document 6]
Japanese Patent Kokai Publication No. JP-A-11-298261
[Patent Document 7]
Japanese Patent No. 3425909